Enhanced Hardware Implementation of Hybrid Stochastic Neural Network using FPGA

Enhanced Hardware Implementation of Hybrid StochasticNeural Network using FPGARafid Ahmed Khalil Mustafa SalimEmail:[emailprotected] Email:[emailprotected]AbstractMost of the traditional digital implemented systems uses fixed point or floatingpoint for representing and processing data. An alternative approach is to represent dataas random bits that are distributed along the sequence. To be precise, stochastic logiccan be considered as a solution for hardware size for application that consume physicalarea like neural networks as it uses logic gates to implement complex operations and itsinherits resistance to bit flips noise. To avoid some of the problems that this type ofprocessing suffers from, a combination of stochastic logic and classical logic (fixed point)is used to implement a neural networks (Fully connected feed-forwards) that ischaracterized by FPGA large size consuming. The stochastic logic is utilized have toimplement part of the multiplication operations in the hidden layers of network andLFSR is used as a random generator for conversion of weights and activation functionsoutputs. The hardware utilization of Spartan 3E-500K FPGA results are compared withanother network of the same size. A discussion of some of the issues that related to thismethodology faces is also presented.Key words: Artificial neural networks, LFSR, Probabilistic computation, Stochasticarithmetic, FPGA, Stochastic logic. FPGA , .)bit flips( (Fully connected feed- FPGA forward) (LFSR) . .