Fpga Design And Implementation Of A Scan Conversion Graphical Sub-System

Section: Article
Published
Sep 28, 2008
Pages
80-92

Abstract

AbstractOne Major modeling primitive in the field of Computer Graphics is a planar polygon. This polygon can have an arbitrary number of vertices and different shapes. In this paper a graphic sub-system is designed and implemented using Field Programmable Gate Array ( FPGA ). One of the main tasks of the hardware designed is scan-converting convex planar polygons required to update an image in the image memory or video RAM which is used as a Frame Buffer. A facility to read the pixels (Picture Elements), from the frame buffer, for display on the monitor of the computer is also included in the design.Keywords: frame buffer, scan-conversion, polygons, pixels, FPGA

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How to Cite

[1]
A. I. Dawod and F. H. Ali, “Fpga Design And Implementation Of A Scan Conversion Graphical Sub-System”, AREJ, vol. 16, no. 4, pp. 80–92, Sep. 2008.