Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method

Design and FPGA Implementation of Two-DimensionalDiscrete Wavelet Transform Architectures Using Raster-ScanMethodJassim M. Abdul-Jabbar Zahraa Talal Abed Al-MokhtarDept. of Computer Eng., College of Eng., University of Mosul, Mosul, Iraq[emailprotected] [emailprotected]AbstractIn this paper, an FPGA implementation of a 2-dimenional discrete wavelettransform (2-D DWT) is proposed to efficiently construct the corresponding twodimensionalarchitecture by using the raster-scan image method for any givenhardware architecture of one dimensional (1-D) wavelet transform filter. Theproposed method is based on lifting scheme architecture. The resulting architecturesare simple, modular and regular for computation of one or multilevel 2-D DWT.These architectures perform both low pass and high pass filter with multiplierlesscoefficients calculation. In addition they require a small on-chip area to download thearchitectures on FPGA Board (Spartan-3E). The proposed 2-D architecture consistsof: external memory, Row 1-D arithmetic module, column 1-D arithmetic module andinternal memory unit. The row and column 1-D arithmetic units are designedutilizing Biorthogonal filters (5/3 and 9/7).Keywords: 2-D DWT, FPGA implementation, Lifting scheme architecture, Rasterscanmethod. FPGA . - - [emailprotected] [emailprotected]FPGA 2- ) D DWT( 1- (. D( . 2- ) D DWT) . : .(Spartan-3E) FPGA 9) .