Single Chip DWT-IDWT Processor Design with VHDL

Abstract: frames under C.LThe applications of Discrete Wavelet Transform necessitate fast computation. Full-customVLSI devices (ASIC) have been used for fast though expensive implementations of DWT.Field-Programmable Gate Array (FPGA) architectures offer economical but area-constrainedimplementation of DWT. The present paper proposes an important issues on the design andsimulation of ASIC and FPGA architectures for 1-D DWT as well as inverse DWT on asingle chip using VHDL simulation tools. The design of the programmable chip that can beused as 1-D DWT or IDWT is introduced based on two quadrature mirror filters (QMF), oneused with DWT (decomposition) and other used with IDWT. The design is modular; the chipcan easily be worked as DWT or IDWT with ability of selecting one of the fourcorresponding types of QMF wavelet filters (Daubechies 1, 2, 3 and 4).The first chip is implemented and simulated using FPGA for two word lengths 8-bit and12-bit respectively. The results show a clock speed of 66.2 MHz for 8-bit, and 55 MHz for12-bit. While the design of ASIC chip validate a clock speeds 85.5 MHz and 59.2 MHz for8-bit and 12-bit respectively. Simulation results have established that the higher word lengthincrease accuracy but at the expense of higher designed size and longest combinational logicbetween two storage elements. This means increasing the length of critical path as result ofcomplexity which decrease the maximum speed clock.Keywords: VHDL, Wavelet, FPGA, Architecture.