Complexity Reduction and Performance Improvement of Multistage Detector with Parallel Interference Cancellation for DS-CDMA System

AbstractIn this paper we propose a new method which combines the partial cancellation and differencing technique to achieve performance improvement and reduction in complexity, the proposed technique is named Multistage (DP-PIC) Detector. The simulation model for the proposed DP-PIC is implemented in floating and fixed point arithmetic. The simulation results illustrates that a partial cancellation factor of 0.7 and 0.8 in the first and second stage respectively gives a good performance for the proposed technique. A precision of 16-bit is enough to achieve a small performance degradation compared to floating point results. Finally the proposed fixed point DP-PIC is implemented on TMS320C6400 DSP simulator. The implementation results illustrate that 35% complexity reduction can be achieved compared with conventional PIC detection.Keywords: DS-CDMA, PIC, Complexity reduction, performance improvement.